The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83B requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level.

The SN75LVDS83B is characterized for operation over ambient air temperatures of –10°C to 70°C.

Alternative device option: The SN75LVDS83A (SLLS980) is an alternative to the SN75LVDS83B for clock frequency range of 10MHz-100MHz only. The SN75LVDS83A is available in the TSSOP package option only.

• LVDS Display Series Interfaces Directly to LCD Display Panels With Integrated LVDS
• Package Options: 4.5-mm × 7-mm BGA, and 8.1-mm × 14-mm TSSOP
• 1.8-V Up to 3.3-V Tolerant Data Inputs to Connect Directly to Low-Power, Low-Voltage Application and Graphic Processors
• Transfer Rate up to 135 Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10 MHz to 135 MHz
• Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI
• Operates From a Single 3.3-V Supply and 170 mW (Typ.) at 75 MHz
• 28 Data Channels Plus Clock in Low-Voltage TTL to 4 Data Channels Plus Clock Out Low-Voltage Differential
• Consumes Less Than 1 mW When Disabled
• Selectable Rising or Falling Clock Edge Triggered Inputs
• ESD: 5-kV HBM
• Support Spread Spectrum Clocking (SSC)
• Compatible with all OMAP? 2x, OMAP? 3x, and DaVinci? Application Processors

• Operating temperature range (C)
• -10 to 70

SN75LVDS83B的完整型号有：SN75LVDS83BDGG、SN75LVDS83BDGGR，以下是这些产品的关键参数及官网采购报价：

SN75LVDS83BDGG，工作温度：-10 to 70，封装：TSSOP (DGG)-56，包装数量MPQ：35个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN75LVDS83BDGG的批量USD价格：2.7（1000+）

SN75LVDS83BDGGR，工作温度：-10 to 70，封装：TSSOP (DGG)-56，包装数量MPQ：2000个，MSL 等级/回流焊峰值温度：Level-2-260C-1 YEAR，引脚镀层/焊球材料：NIPDAU，TI官网SN75LVDS83BDGGR的批量USD价格：2.25（1000+）

EVMX777G-01-20-00 — J6Entry/RSP 信息娱乐（CPU + 显示屏 + JAMR3）评估模块

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主 CPU 板集成了以太网或 HDMI 等主要外设，而信息娱乐应用子板 (JAMR3) 和 LCD/TS 子板将补充 CPU 板，从而提供完整的系统以快速开始评估和应用开发。

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SN75LVDS83B 变送器在单个集成电路中包含 4 个 7 位并行负载串行输出相移寄存器、1 个 7X 时钟合成器以及 5 个低电压差动信号 (LVDS) 线路驱动器。借助这些功能，可通过 5 个平衡对导体将 28 位单端 LVTTL 数据同步发送至兼容接收器，如 SN75LVDS82 和具有集成 LVDS 接收器的 LCD 面板。该 EVM 同样适用于评估 SN65LVDS93A 和 SN65LVDS93A-Q1 器件。

SN75LVDS83B IBIS Model

PSpice for TI 可提供帮助评估模拟电路功能的设计和仿真环境。此功能齐全的设计和仿真套件使用 Cadence 的模拟分析引擎。PSpice for TI 可免费使用，包括业内超大的模型库之一，涵盖我们的模拟和电源产品系列以及精选的模拟行为模型。

借助?PSpice for TI 的设计和仿真环境及其内置的模型库，您可对复杂的混合信号设计进行仿真。创建完整的终端设备设计和原型解决方案，然后再进行布局和制造，可缩短产品上市时间并降低开发成本。

在?PSpice for TI 设计和仿真工具中，您可以搜索 TI (...)

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TINA-TI 安装需要大约 500MB。直接安装，如果想卸载也很容易。我们相信您肯定会爱不释手。

TINA 是德州仪器 (TI) 专有的 DesignSoft 产品。该免费版本具有完整的功能，但不支持完整版 TINA 所提供的某些其他功能。

如需获取可用 TINA-TI 模型的完整列表，请参阅：SpiceRack - 完整列表

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