The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

• Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x? (TMS320C6211 and TMS320C6211B)
  • Eight 32-Bit Instructions/Cycle
  • C6211, C6211B, C6711, and C6711B are Pin-Compatible
  • 150-, 167-MHz Clock Rates
  • 6.7-, 6-ns Instruction Cycle Time
  • 1200, 1333 MIPS
  • Extended Temperature Device (C6211B)
• VelociTI? Advanced Very Long Instruction Word (VLIW) C62x? DSP Core (C6211/11B)
  • Eight Highly Independent Functional Units:
    • Six ALUs (32-/40-Bit)
    • Two 16-Bit Multipliers (32-Bit Results)
  • Load-Store Architecture With 32 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
• Instruction Set Features
  • Byte-Addressable (8-, 16-, 32-Bit Data)
  • 8-Bit Overflow Protection
  • Saturation
  • Bit-Field Extract, Set, Clear
  • Bit-Counting
  • Normalization
• L1/L2 Memory Architecture
  • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
  • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
  • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
• Device Configuration
  • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
  • Endianness: Little Endian, Big Endian
• 32-Bit External Memory Interface (EMIF)
  • Glueless Interface to Asynchronous Memories: SRAM and EPROM
  • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
  • 512M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
• 16-Bit Host-Port Interface (HPI)
  • Access to Entire Memory Map
• Two Multichannel Buffered Serial Ports (McBSPs)
  • Direct Interface to T1/E1, MVIP, SCSA Framers
  • ST-Bus-Switching Compatible
  • Up to 256 Channels Each
  • AC97-Compatible
  • Serial-Peripheral-Interface (SPI) Compatible (Motorola?)
• Two 32-Bit General-Purpose Timers
• Flexible Phase-Locked-Loop (PLL) Clock Generator
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
• 0.18-μm/5-Level Metal Process
  • CMOS Technology
• 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. All trademarks are the property of their respective owners. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

• DSP
• 1 C62x
• DSP MHz (Max)
• 150, 167
• CPU
• 32-/64-bit
• Rating
• Catalog

TMS320C6211B的完整型号有：TMS320C6211BGFN150、TMS320C6211BZFN150、TMS320C6211BZFN167、TMS32C6211BGFNA150、TMS32C6211BZFNA150，以下是这些产品的关键参数及官网采购报价：

TMS320C6211BGFN150，工作温度：PropertyValue，封装：BGA (GFN)-256，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS320C6211BGFN150的批量USD价格：22.088（1000+）

TMS320C6211BZFN150，工作温度：PropertyValue，封装： (ZFN)-256，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-4-260C-72HRS，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6211BZFN150的批量USD价格：22.088（1000+）

TMS320C6211BZFN167，工作温度：PropertyValue，封装： (ZFN)-256，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-4-260C-72HRS，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6211BZFN167的批量USD价格：27.61（1000+）

TMS32C6211BGFNA150，工作温度：PropertyValue，封装：BGA (GFN)-256，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS32C6211BGFNA150的批量USD价格：26.506（1000+）

TMS32C6211BZFNA150，工作温度：PropertyValue，封装： (ZFN)-256，包装数量MPQ：40个，MSL 等级/回流焊峰值温度：Level-4-260C-72HRS，引脚镀层/焊球材料：SNAGCU，TI官网TMS32C6211BZFNA150的批量USD价格：26.506（1000+）

FAXLIB — 用于 C66x、C64x+ 和 C55x 处理器的传真库 (FAXLIB)

C62x/64x FastRTS Library 是优化型浮点函数库，适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用，在这些应用中，提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library，可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

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TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

C6211B GFN Rev 3.0 BSDL Model (Rev. B)

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