The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.

TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

• Highest-Performance Fixed-Point DSPs
  • 1.67-/1.39-/1.17-/1-ns Instruction Cycle
  • 600-/720-/850-MHz, 1-GHz Clock Rate
  • Eight 32-Bit Instructions/Cycle
  • Twenty-Eight Operations/Cycle
  • 4800, 5760, 6800, 8000 MIPS
  • Fully Software-Compatible With C62x?
  • C6414/15/16 Devices Pin-Compatible
  • Extended Temperature Devices Available
• VelociTI.2? Extensions to VelociTI? Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x? DSP Core
  • Eight Highly Independent Functional Units With VelociTI.2? Extensions:
    • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
    • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
  • Non-Aligned Load-Store Architecture
  • 64 32-Bit General-Purpose Registers
  • Instruction Packing Reduces Code Size
  • All Instructions Conditional
• Instruction Set Features
  • Byte-Addressable (8-/16-/32-/64-Bit Data)
  • 8-Bit Overflow Protection
  • Bit-Field Extract, Set, Clear
  • Normalization, Saturation, Bit-Counting
  • VelociTI.2? Increased Orthogonality
• VCP [C6416T Only]
  • Supports Over 833 7.95-Kbps AMR
  • Programmable Code Parameters
• TCP [C6416T Only]
  • Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations)
  • Programmable Turbo Code and Decoding Parameters
• L1/L2 Memory Architecture
  • 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
  • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
  • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
• Two External Memory Interfaces (EMIFs)
  • One 64-Bit (EMIFA), One 16-Bit (EMIFB)
  • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
  • 1280M-Byte Total Addressable External Memory Space
• Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
• Host-Port Interface (HPI)
  • User-Configurable Bus Width (32-/16-Bit)
• 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T]
  • Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O
  • Four-Wire Serial EEPROM Interface
  • PCI Interrupt Request Under DSP Program Control
  • DSP Interrupt Via PCI I/O Cycle
• Three Multichannel Buffered Serial Ports
  • Direct Interface to T1/E1, MVIP, SCSA Framers
  • Up to 256 Channels Each
  • ST-Bus-Switching-, AC97-Compatible
  • Serial Peripheral Interface (SPI) Compatible (Motorola?)
• Three 32-Bit General-Purpose Timers
• UTOPIA [C6415T/C6416T]
  • UTOPIA Level 2 Slave ATM Controller
  • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
  • User-Defined Cell Format up to 64 Bytes
• Sixteen General-Purpose I/O (GPIO) Pins
• Flexible PLL Clock Generator
• IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
• 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 3.3-V I/Os, 1.1-V Internal (600 MHz)
• 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz)

C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture. C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments. Motorla is a registered trademark of the Motorola, Inc.

• DSP
• 1 C64x
• DSP MHz (Max)
• 600, 720, 850, 1000
• CPU
• 32-/64-bit
• Operating system
• DSP/BIOS
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 105, 0 to 90

TMS320C6414T的完整型号有：TMS320C6414TBCLZ1、TMS320C6414TBCLZ6、TMS320C6414TBCLZ7、TMS320C6414TBCLZ8、TMS320C6414TBCLZA6、TMS320C6414TBGLZ1、TMS320C6414TBGLZ6、TMS320C6414TBGLZ7、TMS320C6414TBGLZA6、TMS320C6414TBGLZA7、TMS320C6414TBGLZA8，以下是这些产品的关键参数及官网采购报价：

TMS320C6414TBCLZ1，工作温度：0 to 90，封装：FCBGA (CLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-260C-72 HR，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6414TBCLZ1的批量USD价格：159.486（1000+）

TMS320C6414TBCLZ6，工作温度：0 to 90，封装：FCBGA (CLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-260C-72 HR，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6414TBCLZ6的批量USD价格：65.363（1000+）

TMS320C6414TBCLZ7，工作温度：0 to 90，封装：FCBGA (CLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-260C-72 HR，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6414TBCLZ7的批量USD价格：81.704（1000+）

TMS320C6414TBCLZ8，工作温度：0 to 90，封装：FCBGA (CLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-260C-72 HR，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6414TBCLZ8的批量USD价格：120.268（1000+）

TMS320C6414TBCLZA6，工作温度：-40 to 105，封装：FCBGA (CLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-260C-72 HR，引脚镀层/焊球材料：SNAGCU，TI官网TMS320C6414TBCLZA6的批量USD价格：78.436（1000+）

TMS320C6414TBGLZ1，工作温度：0 to 90，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：Call TI，TI官网TMS320C6414TBGLZ1的批量USD价格：159.486（1000+）

TMS320C6414TBGLZ6，工作温度：0 to 90，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：Call TI，TI官网TMS320C6414TBGLZ6的批量USD价格：65.363（1000+）

TMS320C6414TBGLZ7，工作温度：0 to 90，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS320C6414TBGLZ7的批量USD价格：81.704（1000+）

TMS320C6414TBGLZA6，工作温度：-40 to 105，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS320C6414TBGLZA6的批量USD价格：78.436（1000+）

TMS320C6414TBGLZA7，工作温度：-40 to 105，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS320C6414TBGLZA7的批量USD价格：94.776（1000+）

TMS320C6414TBGLZA8，工作温度：-40 to 105，封装：FCBGA (GLZ)-532，包装数量MPQ：60个，MSL 等级/回流焊峰值温度：Level-4-220C-72 HR，引脚镀层/焊球材料：SNPB，TI官网TMS320C6414TBGLZA8的批量USD价格：133.341（1000+）

TMDSDSK6416 — TMS320C6416 DSP 入门套件 (DSK)

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)

芯片支持库 (CSL) 提供了一个应用程序编程接口 (API)，用于配置和控制 DSP 片上外设，以实现易用性、各种 C6000 器件间的兼容性以及硬件抽象。通过本身的标准性和可移植性，可缩短开发时间。特性部分中列出的功能专为以下器件设计：C6201、C6202、C6203、C6204、C6205、C6211、C6410、C6412、C6413、C6414、C6415、C6416、C6418、C6701、C6711、C6712、C6713、DA610、DM640、DM641 和 DM642。特性模块名称外设说明高速缓存高速缓存DAT与器件无关的数据复制/填充DMA直接存储器访问EDMA (...)

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库，适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用，在这些应用中，提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library，可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性 单精度和双精度数学函数 单精度和双精度转换函数 浮点加法 将浮点值转换为 32 位带符号整数值 将 32 位带符号整数值转换为浮点值 (...)

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library- VoLIBprovides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

C6414T, C6415T, C6416T GLZ BSDL Model Version 1.1

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)