The Texas Instruments XIO3130 switch is a PCI Express ×1 3-port fanout switch. The XIO3130 provides a single ×1 upstream port supporting full 250-MB/s packet throughput in each direction simultaneously. Three independently configurable ×1 downstream ports are provided that also support full 250-MB/s packet throughput in each direction simultaneously.

A cut-through architecture is implemented to reduce the latency associated with packets moving through the PCI Express fabric. As soon as the address or routing information is decoded within the header of a packet entering an ingress port, the packet is directed to the egress port for forwarding. Packet poisoning using the EDB framing signal is supported in circumstances where packet errors are detected after the transmission of the egress packet begins.

The downstream ports may be configured to support PCI Hot Plug slot implementations. In this scenario, the system designer may decide to use the integrated PCI Hot Plug-compliant controller. This feature is available through the classic PCI configuration space under the PCI Express Capability Structure. When enabled, the downstream ports provide the PCI Hot Plug standard mechanism to apply and remove power to the slot or socket.

Power-management features include Active State Power Management, PME mechanisms, the Beacon/Wake protocol, and all conventional PCI D-states. When ASPM is enabled, each link automatically saves power when idle using the L0s and L1 states. PME messages are supported along with the PME_Turn_Off/PME_TO_Ack protocol.

When enabled, the upstream port supports Beacon transmission as well as the WAKE side band signal to wake the system as the result of a PCI Hot Plug event. Furthermore, the downstream ports may be configured to detect Beacon from downstream devices and forward this upstream. The switch also supports the translation and forwarding of WAKE from a downstream device into Beacon on the upstream port for cabled implementations.

• PCI Express Base Specification, Revision 1.1
• PCI Express Card Electromechanical Specification, Revision 1.1
• PCI-to-PCI Bridge Architecture Specification, Revision 1.1
• PCI Bus Power Management Interface Specification, Revision 1.2
• PCI Express Fanout Switch With One ×1 Upstream Port and Three ×1 Downstream Ports
• Packet Transmission Starts While Reception Still in Progress (Cut-Through)
• 256-Byte Maximum Data Payload Size
• Peer-to-Peer Support
• Wake Event and Beacon Support
• Support for D1, D2, D3hot, and D3cold
• Active State Power Management (ASPM) Using Both L0s and L1
• Low-Power PCI Express Transmitter Mode
• Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
• Integrated PCI Hot Plug Support
• Integrated REFCLK Buffers for Switch Downstream Ports
• 3.3-V Multifunction I/O Pins for PCI Hot Plug Status and Control or General Purpose I/Os
• Optional Serial EEPROM for System-Specific Configuration Register Initialization

PCI Express, PCI Hot Plug are trademarks of others.

• Type
• Packet switch
• Protocols
• PCIe
• Applications
• PCIe
• Number of channels (#)
• 4
• Speed (Max) (Gbps)
• 2.5
• Supply voltage (V)
• 1.5, 3.3
• Rating
• Catalog
• Operating temperature range (C)
• -40 to 85, 0 to 70

XIO3130的完整型号有：XIO3130INMH、XIO3130NMH，以下是这些产品的关键参数及官网采购报价：

XIO3130INMH，工作温度：-40 to 85，封装：NFBGA (NMH)-196，包装数量MPQ：126个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：SNAGCU，TI官网XIO3130INMH的批量USD价格：9.741（1000+）

XIO3130NMH，工作温度：0 to 70，封装：NFBGA (NMH)-196，包装数量MPQ：126个，MSL 等级/回流焊峰值温度：Level-3-260C-168 HR，引脚镀层/焊球材料：SNAGCU，TI官网XIO3130NMH的批量USD价格：8.47（1000+）

XIO3130EVM — XIO3130EVM 评估模块

The Texas Instruments XIO3130 EVM is a functional implementation of a four-port PCIe-to-PCIe switch. The XIO3130 EVM was designed to allow validation of three separate functional modes. In normal mode the EVM is configures as a generic PCI Express switch. In Hot Plug modedownstream ports 1 and 2 (...)

XIO3130 IBIS Model

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